This invention relates generally to integrated comparator circuits, and more particularly to a comparator circuit which prevents substrate injection when the input voltage falls below substrate ground.
A well known comparator circuit includes first and second differential input transistors for use in conjunction with a current mirror circuit. The base terminal of the first transistor is typically coupled to receive a reference voltage (V.sub.REF) while the base terminal of the second transistor is coupled to receive an input voltage (V.sub.IN). The state of the comparator's output then depends on the relative magnitudes of V.sub.REF and V.sub.IN.
Such comparator circuits are commonly implemented in epitaxial wells (e.g. N-type) formed on a semiconductive substrate (e.g. P-type). If the input transistors are lateral PNP transistors, a parasitic diode exists between the substrate and the base epitaxial region. Should V.sub.IN fall below the substrate ground, as is possible in many automotive applications, the parasitic diode becomes forward biased resulting in substrate injection; i.e. current being pulled from another epitaxial island (epi-island). If this epi-island contained a sensitive logic node, the unwanted substrate injection could result in an improper logic state.